Zero-Voltage Zero-Current Soft Switching Type Driving Method for Ultrasonic Driving Unit

ABSTRACT

A zero-voltage zero-current soft switching type driving method for an ultrasonic motor is provided, relating to the technical field of driving of a two-phase actuator. The disclosure solves the problems of high loss, high heat amount and the like in a traditional ultrasonic motor driving circuit. The method provided realizes resonance between series inductors and buffer capacitors by means of an optimal design of the inductance of matching inductors, the capacitance of buffer capacitors, a dead time value and a delay time value, thereby causing a power tube to realize zero-voltage and zero-current switching. Two signal input ends of a two-phase pseudo full bridge inverter are connected to a power grid, and two signal output ends of the two-phase pseudo full bridge inverter are respectively connected to two signal input ends of a matching circuit; and the output ends of the matching circuit are respectively connected to a two-phase ultrasonic motor.

TECHNICAL FIELD

The disclosure relates to a driving technology of a two-phase actuator, in particular, an inverter circuit and a control method used for controlling a two-phase ultrasonic motor and having the soft switching capability. The solutions of the disclosure are particularly applicable to an optimal design of a two-phase ultrasonic motor driving circuit.

BACKGROUND

A driving technology of an existing ultrasonic motor usually depends on an inverter. With the emergence of ultrasonic motors and the expansion of the range of application, the problems in the existing driving technology are increasingly prominent in the application of an ultrasonic motor system.

A two-phase ultrasonic motor is a novel two-phase actuator. Compared with a traditional two-phase electromagnetic motor, the ultrasonic motor has many advantages in terms of high displacement sensitivity, high positioning accuracy, large static torque when an input power is cut off and the like. Therefore, the ultrasonic motor is considered to be a superior alternative to the traditional electromagnetic motor in many industrial applications, especially in precise positioning applications. However, in order to cause the ultrasonic motor to operate normally, a voltage frequency required by the ultrasonic motor is usually relatively high, which is generally 20 kHz or more and much greater than the normal operating frequency of the electromagnetic motor. Such a high operating frequency poses a challenge to the design of a frequency converter. Inverters widely used in ultrasonic motors include full-bridge and push-pull inverters. Under the same design specifications, a bus voltage of the push-pull inverter is several times higher than the bus voltage of the full-bridge inverter, which causes losses and limits the energy transmission efficiency of a driver. The loss introduced by a transformer is greater than the loss introduced by an additional switch tube in the full-bridge inverter.

In summary, the relatively high switching loss restricts the improvement of the performance of an ultrasonic motor driving circuit, which in turn limits the application of the ultrasonic motor system to a certain extent.

SUMMARY

The disclosure is directed to solve the problems of high loss, large volume, low efficiency and the like of an ultrasonic motor driving circuit designed by a traditional inverter topology structure. A zero-voltage zero-current soft switching type driving method for an ultrasonic motor consists of a two-phase pseudo full bridge inverter circuit (101) having the soft switching capability, a matching circuit (102), and specific matching inductance, buffer capacitance, and dead time and delay time calculation methods.

The two-phase pseudo full bridge inverter circuit having the soft switching capability is characterized in that the two-phase pseudo full bridge inverter circuit (101) having the soft switching capability consists of six power switch tubes, including a first MOS tube (Q₁), a second MOS tube (Q₂), a third MOS tube (Q₃), a fourth MOS tube (Q₄), a fifth MOS tube (Q₅), a sixth MOS tube (Q₆), a first buffer capacitor (C_(Q2)), a second buffer capacitor (C_(Q4)), a first transformer (T_(A)) and a second transformer (T_(B)).

The drain of the first MOS tube (Q₁), the drain of the third MOS tube (Q₃) and the drain of the fifth MOS tube (Q₅) are connected, and then are connected to a positive pole of a direct current bus of the two-phase pseudo full bridge inverter circuit (101);

the source of the second MOS tube (Q₂), the source of the fourth MOS tube (Q₄), the source of the sixth MOS tube (Q₆), one end of the first buffer capacitor (C_(Q2)) and one end of the second buffer capacitor (C_(Q4)) are connected, and then are connected to a negative pole of the direct current bus of the two-phase pseudo full bridge inverter circuit (101);

the source of the first MOS tube (Q₁), the drain of the second MOS tube (Q₂), the other end of the first buffer capacitor (C_(Q2)) and one end of a primary winding of the first transformer (T_(A)) are connected, and an end, having the same name as the end, of a secondary winding of the first transformer (T_(A)) is used as a first voltage output end of the two-phase pseudo full bridge inverter circuit (101);

the source of the fifth MOS tube (Q₅), the drain of the sixth MOS tube (Q₆), the other end of the second buffer capacitor (C_(Q4)) and one end of a primary winding of the second transformer (T_(B)) are connected, and an end, having the same name as the end, of a secondary winding of the second transformer (T_(B)) is used as a second voltage output end of the two-phase pseudo full bridge inverter circuit (101);

the source of the third MOS tube (Q₃), the drain of the fourth MOS tube (Q₄), the other end of the primary winding of the first transformer (T_(A)) and the other end of the primary winding of the second transformer (T_(B)) are connected, and the other end of the secondary winding of the first transformer (T_(A)) is connected to the other end of the secondary winding of the second transformer (T_(B)) to form a third voltage output end of the two-phase pseudo full bridge inverter circuit (101);

a voltage between the first voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as one phase of input voltage of a two-phase motor;

a voltage between the second voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as the other phase of input voltage of the two-phase electromagnetic motor.

According to the zero-voltage zero-current soft switching type driving method for the ultrasonic motor, the matching circuit (102) includes a first inductor (L_(A)) and a second inductor (L_(B));

the first voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the first inductor (L_(A)), and the other end of the first inductor (L_(A)) is used as a first voltage output end of the matching circuit (102);

the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as a third voltage output end of the matching circuit (102);

the second voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the second inductor (L_(B)), and the other end of the second inductor (L_(B)) is used as a second voltage output end of the matching circuit (102);

a voltage between the first voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as a two-phase voltage of a two-phase ultrasonic motor/piezoelectric sensor;

a voltage between the second voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as the other two-phase signal of the two-phase ultrasonic motor/piezoelectric sensor.

According to the zero-voltage zero-current soft switching type driving method for the ultrasonic motor, a calculation method of the inductance of the first inductor (L_(A)) and the inductance of the second inductor (L_(B)) in the matching circuit (102) is as follows:

in the matching circuit (102), the first inductor (L_(A)) and the second inductor (L_(B)) are both expressed by inductance L:

L=(C _(d) R _(m) ² L _(m) C _(m)/(L _(m) C _(m) +C _(d) ² R _(m) ²))×(1+α_(L)),

wherein,

R _(m)=1/(max(G)−min(G)),

L _(m) =R _(m)/[ω(min(B))−ω(max(B))],

C _(m)=1/(L _(m)ω_(r) ²),

C _(d)=(max(B)+min(B))/(2ω_(r)),

wherein α_(L) is a remaining coefficient of inductance; G=|Y|×cos(φ) refers to conductance; B=|Y|×sin(φ) refers to susceptance; |Y| and ω refers to an absolute value and a phase of the admittance, and can be directly measured through an impedance analyzer; ω(.) is a function of an angular frequency under an output (.) condition; and ω_(r) refers to a resonant frequency. The design of the remaining inductance coefficient α_(L) needs to balance a contradiction between the conduction loss and the switching loss; an extremely large α_(L) may cause relatively high conduction loss, and extremely small α_(L) may cause relatively high switching loss; and a typical value of the parameter may be 0.1.

According to the zero-voltage zero-current soft switching type driving method for the ultrasonic motor, a calculation method of the capacitance of the first buffer capacitor (C_(Q2)) and the capacitance of the second buffer capacitor (C_(Q4)) is as follows:

The first buffer capacitor (C_(Q2)) and the second buffer capacitor (C_(Q4)) in the two-phase pseudo full bridge inverter circuit (101) are uniformly expressed by capacitance C:

C>max(10C _(OSS),4/R _(E)ω_(E)),

wherein,

R _(E) =R _(m) L _(m) C _(m)/(n _(T) ²(L _(m) C _(m) +C _(d) ² R _(m) ²)),

ω_(E)=1/(α_(L) C _(d) R _(m)),

wherein C_(OSS) refers to output capacitance of a power switch; α_(L) is the remaining coefficient of inductance; and n_(T) is a transformer turns ratio;

if a switch with relatively low output capacitance is selected, and the capacitance meets C_(OSS)>>0.4/(R_(E)ω_(E)), the capacitance of C is expressed as: C=4/(R_(E)ω_(E))×(1+α_(C));

wherein α_(C) is a remaining capacitance coefficient; the design of the remaining capacitance coefficient α_(C) needs to balance a contradiction between the conduction loss and the switching loss; an extremely large α_(C) may cause relatively high conduction loss, and extremely small α_(C) may cause relatively high switching loss; and a typical value of the parameter may be 0.1.

The two-phase pseudo full bridge inverter circuit having the soft switching capability is characterized by having specific dead time t_(d) and delay time t_(d/t). The dead time t_(d) is jointly composed of t_(d1) and t_(d2), and may be described as follows:

t _(d) =t _(d1) +t _(d2)=1/ω_(E)+1/(2ω₀);

the delay time t_(dlt) may be described as follows:

t _(dlt) =T _(S)/4−t _(d),

wherein T_(S) is a cycle for outputting current.

The disclosure has the beneficial effects that: the novel two-phase pseudo full bridge inverter topology structure is adopted; two phases of outputs of the two-phase pseudo full bridge inverter topology structure share two bridge arms respectively composed of switches Q₃ and Q₄; the on-off statuses of Q₁ and Q₆ are the same and the on-off statuses of Q₂ and Q₅ are the same, the on-off statuses of Q₃ and Q₄ are approximately opposite, and a time difference is t_(d); each power switch tube is switched on once and only once and switched off once and only once within an inversion cycle; furthermore, it can be seen from FIG. 4 A-D that each phase of pulse width of a two-phase voltage output by the two-phase pseudo full bridge inverter circuit is approximately equal to T_(S)/4, thus realizing zero-voltage or zero-current switching on and switching off. Compared with an existing push-pull driving circuit, the two-phase pseudo full bridge inverter circuit has more operating modes. Compared with an existing full bridge type driving circuit, the quantity of power switch tubes is reduced from eight to six, thereby reducing the complexity of the circuit and lowering the switching loss. A soft switching technology is realized by means of resonance of series inductors and buffer capacitors, thereby greatly reducing the switching loss and realizing a high-efficiency inverter design.

In addition, the two-phase pseudo full bridge inverter circuit having the soft switching capability is connected to different motors due to different electrical characteristics; when the two-phase voltage of the two-phase pseudo full bridge inverter circuit is directly connected to a motor, the two-phase voltage can be connected to an electromagnetic motor; and when the two-phase voltage of the two-phase pseudo full bridge inverter circuit is connected to a motor through the matching circuit, the two-phase voltage can be connected to an ultrasonic motor or a piezoelectric sensor. The two-phase pseudo full bridge inverter circuit having the soft switching capability can be applied to the design of a plurality of two-phase ultrasonic/piezoelectric sensor driving circuits, for example, it can be applied to a driving circuit of a two-phase actuator, such as a rotary type traveling wave ultrasonic motor, a linear type traveling wave ultrasonic motor, a longitudinally torsional compound ultrasonic motor, a two-phase electromagnetic motor and a piezoelectric sensor, and has the advantages of high efficiency, low loss, low cost, stable performance, easy implementation and the like.

BRIEF DESCRIPTION OF FIGURES

FIG. 1 is a schematic diagram of a two-phase pseudo full bridge inverter driving circuit having the soft switching capability;

FIG. 2 is an equivalent circuit diagram of piezoelectric devices of a transformer and a matching inductor;

FIG. 3 is a circuit diagram of the two-phase pseudo full bridge inverter driving circuit shown in FIG. 1 after the two-phase pseudo full bridge inverter driving circuit is subjected to equivalence shown in FIG. 2;

FIG. 4 A-D is an operating circuit of four modes of a two-phase pseudo full bridge inverter driving circuit for operating modes of the negative half-wave cycle of a load current; and

FIG. 5 is a schematic diagram of a waveform when a two-phase output voltage in the two-phase pseudo full bridge inverter driving circuit shown in FIG. 1 is controlled.

DETAILED DESCRIPTION

Specific implementation mode I: A zero-voltage zero-current soft switching type driving method for an ultrasonic motor consists of a two-phase pseudo full bridge inverter circuit (101) having the soft switching capability, a matching circuit (102), and specific matching inductance, buffer capacitance, dead time and delay time calculation methods.

Specific implementation mode II: The present implementation mode is a further description of the zero-voltage zero-current soft switching type driving method for the ultrasonic motor of the specific implementation mode I. The present implementation mode is specifically illustrated with reference to FIG. 1. In a two-phase pseudo full bridge inverter driving circuit having the soft switching capability of the present implementation mode, the two-phase pseudo full bridge inverter circuit (101) consisting of six power switch tubes includes a first MOS tube (Q₁), a second MOS tube (Q₂), a third MOS (Q₃), a fourth MOS tube (Q₄), a fifth MOS tube (Q₅), a sixth MOS tube (Q₆), a first buffer capacitor (C_(Q2)), a second buffer capacitor (C_(Q4)), a first transformer (T_(A)) and a second transformer (T_(B));

a freewheel diode is connected between the drain and the source of each MOS tube;

the drain of the first MOS tube (Q₁), the drain of the third MOS tube (Q₃) and the drain of the fifth MOS tube (Q₅) are connected to form a positive pole of a direct current bus of the two-phase pseudo full bridge inverter circuit (101);

the source of the second MOS tube (Q₂), the source of the fourth MOS tube (Q₄), the source of the sixth MOS tube (Q₆), one end of the first buffer capacitor (C_(Q2)) and one end of the second buffer capacitor (C_(Q4)) are connected to form a negative pole of the direct current bus of the two-phase pseudo full bridge inverter circuit (101);

the source of the first MOS tube (Q₁), the drain of the second MOS tube (Q₂), the other end of the first buffer capacitor (C_(Q2)) and one end of a primary winding of the first transformer (T_(A)) are connected, and an end, having the same name as the end, of a secondary winding of the first transformer (T_(A)) is used as a first voltage output end of the two-phase pseudo full bridge inverter circuit (101);

the source of the fifth MOS tube (Q₅), the drain of the sixth MOS tube (Q₆), the other end of the second buffer capacitor (C_(Q4)) and one end of a primary winding of the second transformer (T_(B)) are connected, and an end, having the same name as the end, of a secondary winding of the second transformer (T_(B)) is used as a second voltage output end of the two-phase pseudo full bridge inverter circuit (101);

the source of the third MOS tube (Q₃), the drain of the fourth MOS tube (Q₄), the other end of the primary winding of the first transformer (T_(A)) and the other end of the primary winding of the second transformer (T_(B)) are connected, and the other end of the secondary winding of the first transformer (T_(A)) is connected to the other end of the secondary winding of the second transformer (T_(B)) to form a third voltage output end of the two-phase pseudo full bridge inverter circuit (101);

a voltage between the first voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as a two-phase voltage of a two-phase electromagnetic motor;

a voltage between the second voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as the other two-phase voltage of the two-phase electromagnetic motor.

In the present implementation mode, it can be seen from FIG. 4 A-D that analysis and mode operations can be only provided for the negative half cycle-line cycle of a load current i_(LEA), because operations in the positive half cycle-line cycle are nearly the same except for the current and switch functions. There are assumptions below: all active power switches are ideal options for parallel body diodes and output capacitances. Compared with the capacitances introduced by the buffer capacitors C_(Q2) and C_(Q4), the output capacitances are low enough, so that the influence of the output capacitances on switch rising and dropping time can be ignored; differences between L_(EA) and L_(EB) as well as between R_(EA) and R_(EB) are ignored, so that their values can be respectively expressed by L_(E) and R_(E); and all other components, except the components in FIG. 4 A-D, are ignored.

In the present implementation mode, for a circuit mode 1 shown in FIG. 4 A-D, i.e., [t₀,t₁]:

When the power switch Q₃ is switched on, mode 1 is initiated. The buffer capacitor C_(Q4) is then charged by Q₃. After a commutation cycle sum of V_(Q4) and the voltage at two ends of the body diodes of Q₃ is completed, the voltage on Q₃ turns into zero from V_(DC) (which is a voltage amplitude value of a direct current voltage signal output end), and the voltage at two ends of the power switch Q₄ is increased from zero to V_(DC). Initial current passing through Q₄ realizes ZCS (zero-current switching) of Q₄ after the commutation cycle. At the beginning of mode 1, i_(Q3) flows through the body diodes of Q₃, and also flows through Q₅, L_(EB) and R_(EB). The current is expressed by i_(DQ3):

i _(L2)(t)=i _(DQ3)(t)=i _(L2)(t)·Ξ(t,t ₀),

wherein,

Ξ[t,x]=1/(1+ω_(E)(t−x))ε[0,1].

After i_(DQ3) reaches zero, since the voltage at two ends of L_(EA) and R_(EA) is the bus voltage V_(DC) i_(Q3) is constantly increased, which is expressed as follows:

i _(L1)(t)=i _(Q3)(t)=V _(DC) /R _(E)·(1−Ξ(t,t ₀)).

In this mode, the current i_(L1) is the same as i_(Q2) and i_(LEA) except polarity, and will reach a maximum value V_(DC)/R_(E). By virtue of L_(EA) and the buffer capacitor C_(Q4), the increase in the current passing through Q₃ is later than the conduction of Q₃. This means that ZVS (zero-voltage switching) of the power switch Q₃ can be realized.

In the present implementation mode, for a circuit mode 2 shown in FIG. 4 A-D, i.e., [t₁,t₂]:

Mode 2 starts from the switching off of the power switches Q₂ and Q₅. The resonance of L_(EA) charges the buffer capacitor C_(Q2) through a loop 1. Buffer capacitor voltage and charging current are approximately described as follows:

i _(L1)(t)=i _(CQ2)(t)=V _(DC) /R _(E)·[(1−ω_(e)(t−t ₁))/(1−ω₀ ²(t−t ₁)²)],

V _(Q2)(t)=V _(DC)·[1−(1−ω_(e)(t−t ₁))/(1−ω₀ ²(t−t ₁)²)],

wherein,

ω₀=1/√{square root over (L _(E) C)}, ω_(e)=1/(R _(E) C).

For simplicity, C=C_(Q2)=C_(Q4). In order to realize overdamping of i_(L1) and V_(Q2), the capacitance of the power switch Q₁ needs to meet the following formula:

C>4/(R _(E)ω_(E)).

Due to the existence of V_(Q1)+V_(Q2)=V_(DC), the voltage at two ends of Q₁ is decreased therewith, and can be expressed as:

V _(Q1)(t)=V _(DC) −V _(Q2)(t)=V _(DC)·[(1−ω_(e)(t−t ₁))/(1−ω₀ ²(t−t ₁)²)].

In the present implementation mode, for a circuit mode 3 shown in FIG. 4 A-D, i.e., [t₂,t₃]:

When the power switches Q₁ and Q₆ are switched on at t₂, mode 3 starts. After the charging of the buffer capacitor C_(Q2) is completed, the voltage at two ends of Q₂ reaches V_(DC). Since the initial current of Q₂ is kept at zero, ZCS of Q₂ can be obtained thereafter. Energy stored in L_(EA) is transferred to R_(EA) through the body diodes of Q₁, and Q₃. In this mode, the current of D_(Q1) is the same as i_(L1), and can be expressed as:

i _(L1)(t)=i _(DQ1)(t)=V _(DC) /R _(E)·Ξ(t,t ₂).

At the same time, the current passing through Q₃, R_(EB), L_(EB) and Q₆ will also be increased, and the current can be expressed as:

i _(L2)(t)=V _(DC) /R _(E)·(1−Ξ(t,t ₂)).

This is the same as i_(Q6). Due to the existence of L_(EB), the increasing process of i_(Q6) is much longer than a communication cycle. The current passing through Q₆ is then small enough to be ignored during the conduction of Q₆, thereby realizing ZVS of Q₆. According to another aspect, switching on of Q₆ causes the voltage at two ends of Q₅ to rise to V_(DC) in the case of keeping the current unchanged. Therefore, ZCS of Q₅ can be realized. In this mode, Q₃ is shared by loops 1 and 2, and the current can be calculated as:

i _(Q3)(t)=i _(L1)(t)+i _(L2)(t)=V _(DC) /R _(E).

In the present implementation mode, for a circuit mode 4 shown in FIG. 4 A-D, i.e., [t₃,t₄]:

In mode 4, Q₃ is switched off. The current passing through Q₁ also flows through L_(EA), R_(EA), L_(EB), R_(EB) and Q₆, and is expressed as:

i _(L1)(t)=i _(Q1)(t)=V _(DC)/2R _(E)·(1−Ξ(t,t ₃)).

Since the voltage at two ends of Q₁ is zero, the ZVS operation of Q₁ can be obtained. Meanwhile, the buffer capacitor C_(Q4) starts to pass through R_(EB), and L_(EB) and Q₆, and is discharged through resonance with L_(EB). The voltage and the discharging current of the capacitor can be expressed as:

V _(CQ4)(t)=V _(DC)·[(ω_(E)(t−t ₃)−1)/(ω₀ ²(t−t ₃)²+ω_(E)(t−t ₃)−1)]

i _(L2)(t)=V _(DC) /L·[(t−t ₃)/(ω₀ ²(t−t ₃)²+ω_(E)(t−t ₃)−1)]

C>4/(R _(E)ω_(E)).

C_(Q4) (t)=i_(L2)(t) needs to be satisfied. According to V_(Q3)+V_(CQ4)=V_(DC), the voltage of Q₃ can be calculated as:

V _(Q3)(t)=V _(DC)·[(ω₀ ²(t−t ₃)²)/(ω₀ ²(t−t ₃)²+ω_(E)(t−t ₃)−1)].

In this mode, Q₆ is shared by loops 1 and 2, and the current can be calculated as:

i _(Q6)(t)=i _(L1)(t)+i _(L2)(t).

In the present implementation mode, for the circuit shown in FIG. 1, the circuit shown in FIG. 3 can be obtained by performing equivalence shown in FIG. 2 on piezoelectric devices of a transformer and a matching inductor, and then is made into an integrated circuit, thereby obtaining an inverter module for driving a two-phase ultrasonic/piezoelectric sensor.

It can be seen from the above example, the disclosure provides an optimization solution for the design of a two-phase ultrasonic motor driver. By the adoption of a two-phase three-level inverter topology structure and a corresponding control method, on the premise of not depending on a high-frequency transformer and not additionally increasing the on and off times of the power switch tubes within a unit electrical cycle, a relatively high bus voltage utilization rate is guaranteed, and the use of a relatively small quantity of power switch tubes is ensured, thereby greatly reducing the switching loss, the volume and the complexity of the driving circuit. This two-phase three-level inverter driving circuit based on six power switch tubes and the control method thereof can be used in a plurality of ultrasonic motor driving systems. In comparison with a current industrially applied mainstream driving circuit, the cost, the volume and the loss will be greatly reduced.

Specific implementation mode III: The present implementation mode is a further description of the two-phase pseudo full bridge inverter driving circuit having the soft switching capability of the specific implementation mode II. In the present implementation mode, a switching control logic applied to the bases of the six power switch tubes is as follows:

The on-off status of the first power switch tube (Q₁) is the same as the on-off status of the sixth power switch tube (Q₆); the on-off statuses of the second power switch tube (Q₂) and the fifth power switch tube (Q₅) are the same; and the on-off statuses of the third power switch tube (Q₃) and the fourth power switch tube (Q₄) are approximately opposite.

Each of the first power switch tube (Q₁), the second power switch tube (Q₂), the third power switch tube (Q₃), the fourth power switch tube (Q₄), the fifth power switch tube (Q₅) and the sixth power switch tube (Q₆) is switched on or switched off once and only once within each inversion cycle.

In the present implementation mode, it can be seen from FIG. 5 that in order to avoid the switching loss from being also correspondingly increased with the increase of the on and off times, each of the six power switch tubes in the two-phase pseudo full bridge inverter driving circuit in FIG. 1 is switched on and switched off once and only once within each electrical signal cycle, thereby ensuring that in the inversion cycle, the on and off times are the same as the on and off times of a power switch in an existing full bridge type driving power supply; at the same time, since the quantity of the power switches is reduced from 8 to 6, the soft switching technology is realized through the resonance of series inductors and buffer capacitors; therefore, compared with a traditional full bridge type driving power supply, the disclosure realizes that the switching loss will be greatly reduced.

Specific implementation mode IV: The present implementation mode is a further description of the zero-voltage zero-current soft switching type driving method for the ultrasonic motor of the specific implementation mode I; the present implementation mode is specifically described with reference to FIG. 1; in the present implementation mode, the zero-voltage zero-current soft switching type driving method for the ultrasonic motor further includes a matching circuit (102);

the matching circuit (102) includes a first inductor (L_(A)) and a second inductor (L_(B));

the first voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the first inductor (L_(A)), and the other end of the first inductor (L_(A)) is used as a first voltage output end of the matching circuit (102);

the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as a third voltage output end of the matching circuit (102);

the second voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the second inductor (L_(B)), and the other end of the second inductor (L_(B)) is used as a second voltage output end of the matching circuit (102);

a voltage between the first voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as a two-phase voltage of a two-phase ultrasonic motor/piezoelectric sensor;

a voltage between the second voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as the other two-phase signal of the two-phase ultrasonic motor/piezoelectric sensor.

In the present implementation mode, according to different electrical characteristics of loads, a connection manner between an output power voltage and a motor is direct connection or connection to the motor via the matching circuit.

When the electrical characteristic of a load is inductive or resistive, the two-phase pseudo full bridge inverter circuit is directly connected to the load, and at the same time, the two-phase pseudo full bridge inverter circuit is connected to an electromagnetic motor.

When the electrical characteristic of a load is capacitive, the two-phase pseudo full bridge inverter circuit is connected to the load through the matching circuit, and the load is a two-phase ultrasonic motor/piezoelectric sensor.

Specific implementation mode V: The present implementation mode is specifically described with reference to FIG. 1. The present implementation mode is a further description of the matching circuit of the specific implementation mode III. A calculation method of the inductance of the first inductor (L_(A)) and the inductance of the second inductor (L_(B)) in the matching circuit (102) is as follows:

in the matching circuit (102), the first inductor (L_(A)) and the second inductor (L_(B)) are both expressed by inductance L:

L=(C _(d) R _(m) ² L _(m) C _(m)/(L _(m) C _(m) +C _(d) ² R _(m) ²))×(1+α_(L)),

wherein,

R _(m)=1/(max(G)−min(G)),

L _(m) =R _(m)/[ω(min(B))−ω(max(B))],

C _(m)=1/(L _(m)ω_(r) ²),

C _(d)=(max(B)+min(B))/(2ω_(r)),

wherein α_(L) is a remaining coefficient of inductance; G=|Y|×cos(φ) refers to conductance; B=|Y|×sin(φ) refers to susceptance; |Y| and φ refers to an absolute value and a phase of the admittance, and can be directly measured through an impedance analyzer; ω(.) is a function of an angular frequency under an output (.) condition; and ω_(r) refers to a resonant frequency. The design of the remaining inductance coefficient α_(L) needs to balance a contradiction between the conduction loss and the switching loss; an extremely large α_(L) may cause relatively high conduction loss, and extremely small α_(L) may cause relatively high switching loss; and a typical value of the parameter may be 0.1.

Specific implementation mode VI: The present implementation mode is specifically described with reference to FIG. 1. The present implementation mode is a further description of the two-phase pseudo full bridge inverter driving circuit having the soft switching capability of the specific implementation mode II or the specific implementation mode III. A calculation of the capacitance of the first buffer capacitor (C_(Q2)) and the capacitance of the second buffer capacitor (C_(Q4)) is as follows:

The first buffer capacitor (C_(Q2)) and the second buffer capacitor (C_(Q4)) in the two-phase pseudo full bridge inverter circuit (101) are uniformly expressed by capacitance C:

C>max(10C _(OSS),4/R _(E)ω_(E)),

wherein,

R _(E) =R _(m) L _(m) C _(m)/(n _(T) ²(L _(m) C _(m) +C _(d) ² R _(m) ²)),

ω_(E)=1/(α_(L) C _(d) R _(m)),

wherein C_(OSS) refers to output capacitance of a power switch; α_(L) is the remaining coefficient of inductance; and n_(T) is a transformer turns ratio;

if a switch with relatively low output capacitance is selected, and the capacitance meets C_(OSS)<<0.4/(R_(E)ω_(E)), the capacitance of C is expressed as:

C=4/(R _(E)ω_(E))×(1+α_(C)),

wherein α_(C) is a remaining capacitance coefficient; the design of the remaining capacitance coefficient α_(C) needs to balance a contradiction between the conduction loss and the switching loss; an extremely large α_(C) may cause relatively high conduction loss, and extremely small α_(C) may cause relatively high switching loss; and a typical value of the parameter may be 0.1.

Specific implementation mode VII: The present implementation mode is specifically described with reference to FIG. 1. The present implementation mode is a further description of the two-phase pseudo full bridge inverter driving circuit having the soft switching capability of the specific implementation mode II or the specific implementation mode III. A calculation method of dead time t_(d) and delay time t_(dlt) is as follows:

The dead time t_(d) is jointly composed of dead time t_(d1) and dead time t_(d2), and can be described as follows:

t _(d) =t _(d1) +t _(d2)=1/ω_(E)+1/(2ω₀);

the delay time t_(dlt) may be described as follows:

t _(dlt) =T _(S)/4−t _(d),

wherein T_(S) is a cycle for outputting current. 

What is claimed is:
 1. A zero-voltage zero-current soft switching type driving method for an ultrasonic driving unit, wherein the ultrasonic driving unit comprises a two-phase pseudo full bridge inverter circuit (101) having soft switching capability, and a matching circuit (102), and the zero-voltage zero-current soft switching type driving method comprises a specific matching inductor inductance calculation step, a buffer capacitor capacitance calculation step, and a dead time and delay time calculation step.
 2. The zero-voltage zero-current soft switching type driving method according to claim 1, wherein the two-phase pseudo full bridge inverter circuit (101) having the soft switching capability comprises six power switch tubes, which comprises a first MOS tube (Q₁), a second MOS tube (Q₂), a third MOS tube (Q₃), a fourth MOS tube (Q₄), a fifth MOS tube (Q₅), a sixth MOS tube (Q₆), a first buffer capacitor (C_(Q2)), a second buffer capacitor (C_(Q4)), a first transformer (T_(A)) and a second transformer (T_(B)); a drain of the first MOS tube (Q₁), a drain of the third MOS tube (Q₃) and a drain of the fifth MOS tube (Q₅) are connected, and then are connected to a positive pole of a direct current bus of the two-phase pseudo full bridge inverter circuit (101); a source of the second MOS tube (Q₂), a source of the fourth MOS tube (Q₄), a source of the sixth MOS tube (Q₆), one end of the first buffer capacitor (C_(Q2)) and one end of the second buffer capacitor (C_(Q4)) are connected, and then are connected to a negative pole of the direct current bus of the two-phase pseudo full bridge inverter circuit (101); a source of the first MOS tube (Q₁), a drain of the second MOS tube (Q₂), the other end of the first buffer capacitor (C_(Q2)) and one end of a primary winding of the first transformer (T_(A)) are connected, and an end, having the same name as the one end of the primary winding, of a secondary winding of the first transformer (T_(A)) is used as a first voltage output end of the two-phase pseudo full bridge inverter circuit (101); a source of the fifth MOS tube (Q₅), a drain of the sixth MOS tube (Q₆), the other end of the second buffer capacitor (C_(Q4)) and one end of a primary winding of the second transformer (T_(B)) are connected, and an end, having the same name as the one end of the primary winding, of a secondary winding of the second transformer (T_(B)) is used as a second voltage output end of the two-phase pseudo full bridge inverter circuit (101); a source of the third MOS tube (Q₃), a drain of the fourth MOS tube (Q₄), the other end of the primary winding of the first transformer (T_(A)) and the other end of the primary winding of the second transformer (T_(B)) are connected, and the other end of the secondary winding of the first transformer (T_(A)) is connected to the other end of the secondary winding of the second transformer (T_(B)) to form a third voltage output end of the two-phase pseudo full bridge inverter circuit (101); a voltage between the first voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as one phase of input voltage of a two-phase motor; and a voltage between the second voltage output end of the two-phase pseudo full bridge inverter circuit (101) and the third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as the other phase of input voltage of the two-phase electromagnetic motor.
 3. The zero-voltage zero-current soft switching type driving method according to claim 2, wherein switching control logic applied to bases of the six power switch tubes is as follows: an on-off status of the first MOS tube (Q₁) is the same as an on-off status of the sixth MOS tube (Q₆); on-off statuses of the second MOS tube (Q₂) and the fifth MOS tube (Q₅) are the same; specific dead time exists between the on-off status of the first MOS tube (Q₁) and the on-off status of the second MOS tube (Q₂); the same specific dead time exists between the third MOS tube (Q₃) and the fourth MOS tube (Q₄); and specific delay time exists between the on-off status of the first MOS tube (Q₁) and the on-off status of the third MOS tube (Q₃); each of the first MOS tube (Q₁), the second MOS tube (Q₂), the third MOS tube (Q₃), the fourth MOS tube (Q₄), the fifth MOS tube (Q₅) and the sixth MOS tube (Q₆) is switched on or switched off once and only once within each inversion cycle.
 4. The zero-voltage zero-current soft switching type driving method according to claim 1, wherein the matching circuit (102) comprises a first inductor (L_(A)) and a second inductor (L_(B)); a first voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the first inductor (L_(A)), and the other end of the first inductor (L_(A)) is used as a first voltage output end of the matching circuit (102); a third voltage output end of the two-phase pseudo full bridge inverter circuit (101) is used as a third voltage output end of the matching circuit (102); a second voltage output end of the two-phase pseudo full bridge inverter circuit (101) is connected to one end of the second inductor (L_(B)), and the other end of the second inductor (L_(B)) is used as a second voltage output end of the matching circuit (102); a voltage between the first voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as a two-phase voltage of a two-phase ultrasonic motor/piezoelectric sensor; a voltage between the second voltage output end of the matching circuit (102) and the third voltage output end of the matching circuit (102) is used as the other two-phase signal of the two-phase ultrasonic motor/piezoelectric sensor.
 5. The zero-voltage zero-current soft switching type driving method according to claim 1, wherein a calculation method of inductance of the first inductor (L_(A)) and inductance of the second inductor (L_(B)) in the matching circuit (102) is as follows: in the matching circuit (102), the first inductor (L_(A)) and the second inductor (L_(B)) are both expressed by inductance L: L=(C _(d) R _(m) ² L _(m) C _(m)/(L _(m) C _(m) +C _(d) ² R _(m) ²))×(1+α_(L)), wherein, R _(m)=1/(max(G)−min(G)), L _(m) =R _(m)/[ω(min(B))−ω(max(B))], C _(m)=1/(L _(m)ω_(r) ²), C _(d)=(max(B)+min(B))/(2ω_(r)), wherein α_(L) is a remaining inductance coefficient; G=|Y|×cos(φ) refers to conductance; B=|Y|×sin(φ) refers to susceptance; |Y| and φ refer to an absolute value and a phase of the admittance, and are directly measured through an impedance analyzer; ω(.) is a function of an angular frequency under an output (.) condition; ω_(r) refers to a resonant frequency; a remaining inductance coefficient α_(L) is to balance a contradiction between a conduction loss and a switching loss; an extremely large α_(L) causes a relatively high conduction loss, and an extremely small α_(L) causes a relatively high switching loss; and a value of α_(L) is 0.1.
 6. The zero-voltage zero-current soft switching type driving method according to claim 1, wherein a specific calculation method of capacitance of the first buffer capacitor (C_(Q2)) and capacitance of the second buffer capacitor (C_(Q4)) is as follows: the capacitance of the first buffer capacitor (C_(Q2)) and the capacitance of the second buffer capacitor (C_(Q4)) in the two-phase pseudo full bridge inverter circuit (101) are equal, and are expressed by C: C>max(10C _(OSS),4/R _(E)ω_(E)), wherein, R _(E) =R _(m) L _(m) C _(m)/(n _(T) ²(L _(m) C _(m) +C _(d) ² R _(m) ²)), ω_(E)=1/(α_(L) C _(d) R _(m)), wherein C_(OSS) refers to output capacitance of a power switch; α_(L) is a remaining coefficient of inductance; and n_(T) is a transformer turns ratio; if a MOS tube with relatively low output capacitance is selected, and the capacitance meets C_(OSS)«0.4/(R_(E)ω_(E)), then the capacitance of C is expressed as: C=4/(R _(E)ω_(E))×(1+α_(C)), wherein α_(C) is a remaining capacitance coefficient; the remaining capacitance coefficient α_(C) is to balance a contradiction between a conduction loss and a switching loss; an extremely large α_(C) causes a relatively high conduction loss, and an extremely small α_(C) causes a relatively high switching loss; and a value of α_(C) is 0.1.
 7. The zero-voltage zero-current soft switching type driving method according to claim 1, wherein the dead time and delay time calculation step is used to calculate specific dead time t_(d) and delay time t_(dlt); the dead time t_(d) is jointly composed of time t_(d1) and time t_(d2), and is described as follows: t _(d) =t _(d1) +t _(d2)=1/ω_(E)+1/(2ω₀); the delay time t_(dlt) is described as follows: t _(dlt) =T _(S)/4−t _(d), wherein T_(S) is a cycle for outputting a current. 